AVR assembler specificities
Load with "AVRA".
All mnemonics in AVR have a single signature. Therefore, we
don't need any "argtype" suffixes.
Registers are referred to with consts R0-R31. There is
X, Y, Z, X+, Y+, Z+, X-, Y-, Z- for appropriate ops (LD, ST).
XL, XH, YL, YH, ZL, ZH are simple aliases to R26-R31.
Branching works differently. Instead of expecting a byte to be
written after the naked op, branching words expect a displace-
This is because there's bitwise ORing involved in the creation
of the final opcode, which makes z80a's approach impractical.
This makes labelling a bit different too. Instead of expecting
label words after the naked branching op, we rather have label
words expecting branching wordref as an argument. Examples:
' BRTS L2 TO, ( branch forward to L2 )
' RJMP L1 LBL, ( branch backward to L1 )
Model-specific constants must be loaded separately. AVRA
supplies loader words. Here's a list:
Those units contain register constants such as PORTB, DDRB, etc.
Unlike many modern assemblers, they do not include bit
constants. Here's an example use:
DDRB 5 SBI,
PORTB 5 CBI,
R16 TIFR0 IN,
R16 0 ( TOV0 ) SBRS,
ASR COM DEC INC LAC LAS LAT LSR NEG POP PUSH
ROR SWAP XCH
ADC ADD AND CP CPC CPSE EOR MOV MUL OR SBC
ANDI CPI LDI ORI SBCI SBR SUBI
CBI SBI SBIC SBIS
BREAK CL[C,H,I,N,S,T,V,Z] SE[C,H,I,N,S,T,V,Z] EIJMP ICALL
EICALL IJMP NOP RET RETI SLEEP WDR
BLD BST SBRC SBRS
CLR TST LSL LD ST
LBL! LBL, SKIP, TO, FLBL, FLBL! BEGIN, AGAIN? AGAIN, IF, THEN,
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